The use of complementary metal oxide semiconductors (CMOS) in integrated circuits has facilitated reduction in the amount of power required for standard operation and has accordingly allowed chip designers to reduce the standard supply voltage provided to integrated circuits down to a single volt (1 V). At the same time the operational voltages are being scaled down, chip power usage is actually increasing with the greater frequencies and numbers of transistors in high-performance circuits. According to ohm's law (Power=Voltage×Current), if power is increasing while voltage is decreasing, current must be increasing at a high rate to both match the increasing power while compensating for the decrease in voltage. These high current levels place increasing demands on the voltage regulation systems that provide power to the VLSI circuits.
To provide for such voltage regulation, very large scale integrated circuit (VLSI) designers have developed voltage regulation modules (VRMs) that are employed in a system in conjunction with VLSI circuit dies. A conventional arrangement of a voltage regulation system, illustrated in FIG. 1, shows a VRM module 20 placed adjacent to a VLSI circuit die 10, with both the VRM module 20 and the VLSI circuit 10 stacked on a substrate 5. The VLSI 10 and VRM module are equipped with respective heat sinks 15, 25 and are respectively coupled to the substrate via interconnect wires or solder elements 12, 22. The VRM module 20 is connected to the VLSI via interconnect wires that run through the substrate 5. The substrate is in turn coupled to external interfaces (not shown) via solder ball elements 8.
Two problems associated with implementation of voltage regulation in high-performance circuits are on-die di/dt voltage “droops”, which occur when an immediate demand for current at a localized region of the VLSI die causes a sudden drop in the supply voltage; and IR and Ldi/dt voltage drops, which occur as current is transported over interconnect lines between voltage regulation modules (VRMs) and the VLSI die. In the conventional arrangement of FIG. 1, the placement of the VRM module 20 adjacent to the VLSI assembly 10 on the substrate 5 helps minimize the IR and Ldi/dt voltage drops because of the close proximity between the VRM module and the VLSI die. However, optimal voltage regulation using the conventional arrangement can be impaired by power delivery interconnect bottlenecks between the VRM and the VLSI assembly. In addition, adjacent placement of the VRM module and the VLSI assembly concentrates VRM functionality in a single location, which can cause sub-optimal use of the resources of the VRM system.